When speed is an important requirement, digital processing and storage circuits often use a Static Random Access Memory (SRAM), which, in contrast to a Dynamic Random Access Memory (DRAM), does not need to be periodically refreshed.
An SRAM includes arrays of individual SRAM cells. Each cell is addressed and accessed so that it may be “read” from or “written” to. Each cell includes a pair of cross-coupled inverters that store either a “high” or “low” voltage level. The cross-coupled inverters are coupled with a pass gate, such as a transistor to bit lines, that allows the cross-coupled inverters to be read from or written to. Unfortunately, in radiation environments, such as space and aerospace, the data state held by these cross-coupled inverters and other transistors are susceptible to upset from radiation events.
Because SRAM cells are made from semiconductor materials, such as silicon, a radiation event, such as a particle strike, may induce charge. This charge, or glitch, if large enough, may cause a node within the cross-coupled inverters to change state. If the state change results in a bit-flip or a change in state of the SRAM cell, it is referred to as a Single Event Upset (SEU) or a soft error.
One method that circuit and system designers use to prevent radiation events from causing an SEU in an SRAM is to introduce a resistive hardening element in the feedback loop between the two cross coupled inverters of the SRAM cell. The resistive hardening element is generally referred to as a delay element or a delay. Typically, except for during a write, the delay is enabled. When an SEU occurs, the delay increases the response time of a cell by preventing a radiation induced state change from propagating around the feedback loop until the charge deposited from the SEU is dissipated. During a write, however, the delay is disabled. Disabling the delay decreases the propagation time around the feedback loop and therefore, decreases the write time of the cell.
FIG. 1A shows an example SRAM cell 10 in a radiation hardened configuration. SRAM cell 10 includes inverter 12 cross-coupled with inverter 14. Inverter 12 includes Field Effect Transistor (FET) 16 coupled with FET 18. Inverter 14 includes FET 20 coupled with FET 22. The coupled drains of FETs 16 and 18 are coupled to a delay 24. Delay 24 is coupled to the gates of FETs 20 and 22 and it receives delay and bypass signals at a delay input 25.
In operation, data ports 26 and 28 input data signals, where the data signal on data port 28 is an inverse of the data signal on data port 26. To write and read SRAM cell 10, FETs 30 and 32 serve as pass gates that open and close a data path to inverters 12 and 14. Enable inputs 34 receive an enable signal that opens and closes this data path. For instance, when SRAM cell 10 is being written, FETs 30 and 32 open, and write drivers (not shown) use data ports 26 and 28 to communicate a voltage to inverters 12 and 14. On the other hand, when SRAM 10 cell is being read, FETs 30 and 32 also open; instead of receiving a voltage, however, inverters 12 and 14 output a voltage to data ports 26 and 28.
To increase radiation hardness, SRAM cell 10 includes delay element 24 in a feedback loop through the gates and drains of FETS 16-22. Delay 24, when enabled, delays propagation through the loop between a node 36 and a node 38. Delay 24 typically includes elements that can be controlled to increase or decrease the delay time of the feedback loop through delay input 25. FIG. 1B shows circuit elements that delay 24 may include. In this instance, delay 24 includes a FET 46 coupled with a resistance, such as a resistor 48. When FET 46 receives a bypass signal, a signal may then propagate through FET 48 and bypass resistor 48. On the other hand, when FET 46 receives a delay signal, it forces the signal to propagate through resistor 48, and thus increases the delay time of the feedback loop. The delay time of the feedback loop may be tailored by adding additional elements to the delay or bypass paths of the delay 24.
An example of SEU prevention is demonstrated as follows. If the voltage at node 38 is low, for instance, an SEU induced state change may cause the voltage at node 38 to go high. This high voltage will drive node 36 low. Delay 24, however, will continue to hold the gates of FETs 20 and 22 high so that node 38 returns low. Delay 24 effectively delays the switching, or response time, of the cross-coupled inverters. If the response time is greater than the time it takes for the radiation induced charge to dissipate (i.e., the recovery time), SRAM cell 10 has been effectively radiation hardened.
An SRAM includes column and row arrays of SRAM memory cells. Typically, memory cells are grouped together in order to store multiple bits; such a grouping is referred to as a memory word. A memory word contains at least one memory cell, and each memory cell within a memory word share a common write line. Also, each bit within a memory word is accessed by a set of bit lines.
FIG. 2 shows SRAM cell 10 located with a first row and a first column of an SRAM 100. For simplicity, SRAM 100 includes memory words that consist of a single memory cell. In other instances, an SRAM will contain memory words that comprise multiple memory cells. In the example of FIG. 2, SRAM 100 includes bit lines 101-108, word lines 111-114, and write-word lines 121-124. Bit lines 101-108 are coupled to column MUX 130, which is coupled to column lines 131-132. SRAM cell 10, FETs 20 and 22 are respectively coupled to bit lines 101 and 105, enable inputs 34 are coupled to word line 111, and delay input 25 is coupled to write word-line 121. During a write and a read of SRAM cell 10, bit lines 101-105 exchange data through MUX 130 and ultimately with column lines 131-132. During a read, word line 111 carries an enable signal to the pass gates of SRAM cell 10 and to the pass gates of all of the other memory cells that share a row with SRAM cell 10. Mux 130 then selects bit lines 101 and 105 and the data stored at SRAM cell 10 may be communicated to column inputs 131-132. During a write, word line 111 also enables the pass gates of SRAM cell 10 and pass gates of the other memory cells in the first row. The write word-line 121 then carries a bypass signal to SRAM cell 10 (and all of the other memory cells that share a row with SRAM cell 10). Next, a write driver (not shown) drives new data through MUX 130 to the selected bit-lines 101 & 105 and up to SRAM cell 10. Thus, SRAM cell 10 is written.
Unfortunately, because write-word line 121 also communicates the bypass signal to all of the SRAM cells that share a row with SRAM cell 10, all of the other SRAM cells within the row are bypassed and are therefore vulnerable to an SEU.